axi4_lite_if::<PKG>

AXI4-Lite bus interface

Modports:

• master - AXI Master IP

• slave - AXI slave IP

• monitor - Debugging - All signals are declared as input

• write_master - Reduced signal count for master IP that only writes to slave

• read_master - Reduced signal count for master IP that only reads from slave

• write_slave - Reduced signal count for slave IP that only receives writes from master

• read_slave - Reduced signal count for slave IP that only replies to read requests from master

Convenience functions:

• awaddr_ack() = awready && awvalid

• wdata_ack() = wready && wvalid

• bresp_ack() = bready && bvalid

• araddr_ack() = arready && arvalid

• rdata_ack() = rready && rvalid

Instantiation:

inst c: axi4_lite_if::< axi4_lite_pkg::< ADDR_W, DATA_W_BYTES, ID_W > >;

Usage in module definition with modport:

module my_axi4_lite_slave ( aclk: input clock_posedge,
                            aresetn: input reset_sync_low,
                            axi: modport axi4_lite_if::<axi4_lite_pkg::<32, 4, 8>>::slave )
{

}

Note:

The awid, arid, bid and rid signals on the slave* modports are optional. These and are used to connect compatible AXI4-Lite slaves to a full AXI4 interface (AXI ID reflection on slave required).