std

Veryl Standard Library

Version 0.0.1
Repository https://github.com/veryl-lang/std
License MIT OR Apache-2.0

Modules

async_fifo::<S> Asynchronous FIFO
async_handshake::<S> Asynchronous handshake
binary_decoder A binary decoder.
binary_encoder A binary encoder.
counter Value counter
countones
delay Delay input by configured cycle
demux
edge_detector Edge detector
fifo
gray_counter Value counter using Gray Encoding
gray_decoder Converts a Gray encoded bit vector to a binary encoded bit-vector
gray_encoder Converts a binary encoded bit vector to a Gray encoded bit-vector
lfsr_galois
mux
onehot
ram

Module Prototypes

synchronizer

Interfaces

axi3_if::<PKG> ### AXI3 bus interface
axi4_if::<PKG> ### AXI4 bus interface
axi4_lite_if::<PKG> ### AXI4-Lite bus interface

Packages

axi3_config ### AXI3 configuration definitions
axi3_pkg::<ADDR_W, DATA_W_BYTES, ID_W> ### AXI3 bus package
axi4_config ### AXI4 configuration definitions
axi4_lite_config ### AXI4-Lite configuration definitions
axi4_lite_pkg::<ADDR_W, DATA_W_BYTES, ID_W> ### AXI4-Lite bus package
axi4_pkg::<ADDR_W, DATA_W_BYTES, ID_W, AWUSER_W, WUSER_W, BUSER_W, ARUSER_W, RUSER_W> ### AXI4 bus package
selector_pkg
types A package for pre-defined types

Modules

async_fifo::<S> Asynchronous FIFO
async_handshake::<S> Asynchronous handshake
binary_decoder A binary decoder.
binary_encoder A binary encoder.
counter Value counter
countones
delay Delay input by configured cycle
demux
edge_detector Edge detector
fifo
gray_counter Value counter using Gray Encoding
gray_decoder Converts a Gray encoded bit vector to a binary encoded bit-vector
gray_encoder Converts a binary encoded bit vector to a Gray encoded bit-vector
lfsr_galois
mux
onehot
ram

async_fifo::<S>

Asynchronous FIFO

Asynchronous FIFO based on gray-code pointer. Generic parameter S is a module name of synchrinozer.

Generic Parameters

S synchronizer

Parameters

WIDTH u32 Data width
TYPE type Data type
STAGES u32 Stages of synchronizer
DEPTH u32 Depth of FIFO
THRESHOLD u32 Threshold for almost full signal
USE_OUT_DATA_RESET bit Whether output data is reset
INITIAL_OUT_DATA TYPE Reset value of output data
MERGE_RESET bit Whether both reset are merged
RESET_SYNC_STAGES u32 Stages of reset synchronizer

Clock Domains

'd
's

Ports

is_clk input 's clock src clock
is_rst input 's reset src reset
os_almost_full output 's logic FIFO is almost full
os_full output 's logic FIFO is full
is_push input 's logic push to FIFO
is_data input 's TYPE push data
id_clk input 'd clock dst clock
id_rst input 'd reset dst reset
od_empty output 'd logic FIFO is empty
id_pop input 'd logic pop from FIFO
od_data output 'd TYPE src clock src reset FIFO is almost full FIFO is full push to FIFO push data dst clock dst reset FIFO is empty pop from FIFO

async_handshake::<S>

Asynchronous handshake

Asynchronous data transmitter based on handshake protocol. Generic parameter S is a module name of synchrinoizer.

Generic Parameters

S synchronizer

Parameters

WIDTH u32 Data width
TYPE type Data type
STAGES u32 Stages of synchrinoizer
INITIALIZE_DATA_OUT bit Whether output data is reset
INITIAL_DATA_OUT bit<$bits(TYPE)> Reset value of output data
MERGE_RESET bit Whether both reset are merged
RESET_SYNC_STAGES u32 Stages of reset synchronizer

Clock Domains

'd
's

Ports

is_clk input 's clock src clock
is_rst input 's reset src reset
is_valid input 's logic src data is valid
os_ready output 's logic src data is acceptable
is_data input 's TYPE src data
id_clk input 'd clock dst clock
id_rst input 'd reset dst reset
od_valid output 'd logic dst data is valid
id_ready input 'd logic dst data is acceptable
od_data output 'd TYPE src clock src reset src data is valid src data is acceptable src data dst clock dst reset dst data is valid dst data is acceptable

binary_decoder

A binary decoder.

Converts a bit vector from a binary encoding to a bit vector with a unary encoding.

Parameters

BIN_WIDTH u32 Width of the input binary vector

Ports

i_en input logic Enable Signal. Dynamic power is minimzed when not enabled.
i_bin input logic Binary encoded input.
o_unary output logic Unary encoded output.

binary_encoder

A binary encoder.

Transforms a unary encoded value into a binary encoding.

Parameters

UNARY_WIDTH u32 Width of the input unary vector

Ports

i_en input logic Enable Signal. Dynamic power is minimzed when not enabled.
i_unary input logic Unary encoded input.
o_bin output logic Binary encoded output.

counter

Value counter

Parameters

WIDTH u32 Counter width
MAX_COUNT bit Max value of counter
MIN_COUNT bit Min value of counter
INITIAL_COUNT bit Initial value of counter
WRAP_AROUND bit Whether counter is wrap around

Ports

i_clk input clock Clock
i_rst input reset Reset
i_clear input logic Clear counter
i_set input logic Set counter to a value
i_set_value input COUNT Value used by i_set
i_up input logic Count up
i_down input logic Count down
o_count output COUNT Count value
o_count_next output COUNT Count value for the next clock cycle
o_wrap_around output logic Indicator for wrap around

countones

Parameters

W u32

Ports

i_data input logic
o_ones output logic

delay

Delay input by configured cycle

Parameters

DELAY u32 Clock cycle of delay
WIDTH u32 Input/output data width
TYPE type Input/output data type

Ports

i_clk input clock Clock
i_rst input reset Reset
i_d input TYPE Input
o_d output TYPE Output

demux

Parameters

WIDTH u32
DATA_TYPE type
DEFUALT_DATA u32
ENTRIES u32
KIND selector_kind
SELECT_WIDTH u32

Ports

i_select input logic
i_data input DATA_TYPE
o_data output DATA_TYPE

edge_detector

Edge detector

Parameters

WIDTH u32 Data width
INITIAL_VALUE bit Initial value of internal FF

Ports

i_clk input clock Clock
i_rst input reset Reset
i_clear input logic Clear
i_data input logic Data
o_edge output logic Both edges
o_posedge output logic Positive edge
o_negedge output logic Negative edge

fifo

Parameters

WIDTH u32
TYPE type
DEPTH u32
THRESHOLD u32
FLAG_FF_OUT bit
DATA_FF_OUT bit
RESET_RAM bit
RESET_DATA_FF bit
CLEAR_DATA bit
PUSH_ON_CLEAR bit
MATCH_COUNT_WIDTH u32

Ports

i_clk input clock
i_rst input reset
i_clear input logic
o_empty output logic
o_almost_full output logic
o_full output logic
o_word_count output COUNTER
i_push input logic
i_data input TYPE
i_pop input logic
o_data output TYPE

gray_counter

Value counter using Gray Encoding

Parameters

WIDTH u32 Counter width
MAX_COUNT bit Max value of counter (in binary)
MIN_COUNT bit Min value of counter (in binary)
INITIAL_COUNT bit Initial value of counter (in binary)
WRAP_AROUND bit Whether counter is wrap around

Ports

i_clk input clock Clock
i_rst input reset Reset
i_clear input logic Clear counter
i_set input logic Set counter to a value
i_set_value input COUNT Value used by i_set
i_up input logic Count up
i_down input logic Count down
o_count output COUNT Count value
o_count_next output COUNT Count value for the next clock cycle
o_wrap_around output logic Indicator for wrap around

gray_decoder

Converts a Gray encoded bit vector to a binary encoded bit-vector

  • Space Complexity: O(WIDTH log WIDTH)
  • Time Complexity: O(log WIDTH)

Parameters

WIDTH u32 Input and output bit vector width

Ports

i_gray input logic Input Gray encoded Bit Vector
o_bin output logic Output binary encoded Bit Vector such that o_bin[k] = ^o_bin[WIDTH-1:k]

gray_encoder

Converts a binary encoded bit vector to a Gray encoded bit-vector

  • Space Complexity: O(WIDTH)
  • Time Complexity: O(1)

Parameters

WIDTH u32 Input and output bit vector width

Ports

i_bin input logic Input Binary encoded Bit Vector
o_gray output logic Output Gray encoded Bit Vector

lfsr_galois

Parameters

SIZE u32 Size of the LFSR in bits
TAPVEC TAPVEC_T Bit-vector representing the taps of the LFSR. Default values provided for `SIZE` in range [2, 64]

Ports

i_clk input clock Clock
i_en input logic Enable - LFSR shifts only when enabled. Active high.
i_set input logic Flag to set value of LFSR. Active High.
i_setval input logic Value which LFSR is set to when `i_set` is set.
o_val output logic LFSR value.

mux

Parameters

WIDTH u32
DATA_TYPE type
ENTRIES u32
KIND selector_kind

Ports

i_select input logic
i_data input DATA_TYPE
o_data output DATA_TYPE

onehot

Parameters

W u32

Ports

i_data input logic
o_onehot output logic 1'b1 iff i_data contains exactly one set bit
o_zero output logic 1'b1 iff i_data is zero

ram

Parameters

WORD_SIZE u32
ADDRESS_WIDTH u32
DATA_WIDTH u32
DATA_TYPE type
BUFFER_OUT bit
USE_RESET bit
INITIAL_VALUE DATA_TYPE

Ports

i_clk input clock
i_rst input reset
i_clr input logic
i_mea input logic
i_wea input logic
i_adra input logic
i_da input DATA_TYPE
i_meb input logic
i_adrb input logic
o_qb output DATA_TYPE

Module Prototypes

synchronizer

synchronizer

Parameters

WIDTH u32
STAGES u32

Clock Domains

'd
's

Ports

i_clk input 'd clock
i_rst input 'd reset
i_d input 's logic
o_d output 'd logic

Interfaces

axi3_if::<PKG> ### AXI3 bus interface
axi4_if::<PKG> ### AXI4 bus interface
axi4_lite_if::<PKG> ### AXI4-Lite bus interface

axi3_if::<PKG>

AXI3 bus interface

Modports:

  • master - AXI Master IP

  • slave - AXI slave IP

  • monitor - Debugging - All signals are declared as input

  • write_master - Reduced signal count for master IP that only writes to slave

  • read_master - Reduced signal count for master IP that only reads from slave

  • write_slave - Reduced signal count for slave IP that only receives writes from master

  • read_slave - Reduced signal count for slave IP that only replies to read requests from master

Convenience functions:

  • awaddr_ack() = awready && awvalid

  • wdata_ack() = wready && wvalid

  • bresp_ack() = bready && bvalid

  • araddr_ack() = arready && arvalid

  • rdata_ack() = rready && rvalid

Instantiation:

inst b: axi3_if::< axi3_pkg::< ADDR_W, DATA_W_BYTES, ID_W > >;

Usage in module definition with modport:

module my_axi3_slave ( aclk: input clock_posedge,
                       aresetn: input reset_sync_low,
                       axi: modport axi3_if::<axi3_pkg::<32, 4, 8>>::slave ) {

}

axi4_if::<PKG>

AXI4 bus interface

Modports:

  • master - AXI Master IP

  • slave - AXI slave IP

  • monitor - Debugging - All signals are declared as input

  • write_master - Reduced signal count for master IP that only writes to slave

  • read_master - Reduced signal count for master IP that only reads from slave

  • write_slave - Reduced signal count for slave IP that only receives writes from master

  • read_slave - Reduced signal count for slave IP that only replies to read requests from master

Convenience functions:

  • awaddr_ack() = awready && awvalid

  • wdata_ack() = wready && wvalid

  • bresp_ack() = bready && bvalid

  • araddr_ack() = arready && arvalid

  • rdata_ack() = rready && rvalid

Instantiation:

inst a: axi4_if::< axi4_pkg::< ADDR_W, DATA_W_BYTES, ID_W,
                               AWUSER_W, WUSER_W, BUSER_W,
                               ARUSER_W, RUSER_W > >;

Usage in module definition with modport:

module my_axi4_slave ( aclk: input clock_posedge,
                       aresetn: input reset_sync_low,
                       axi: modport axi4_if::<axi4_pkg::<32, 4, 8,
                                                         8, 8, 8,
                                                         8, 8>>::slave ) {

}

axi4_lite_if::<PKG>

AXI4-Lite bus interface

Modports:

  • master - AXI Master IP

  • slave - AXI slave IP

  • monitor - Debugging - All signals are declared as input

  • write_master - Reduced signal count for master IP that only writes to slave

  • read_master - Reduced signal count for master IP that only reads from slave

  • write_slave - Reduced signal count for slave IP that only receives writes from master

  • read_slave - Reduced signal count for slave IP that only replies to read requests from master

Convenience functions:

  • awaddr_ack() = awready && awvalid

  • wdata_ack() = wready && wvalid

  • bresp_ack() = bready && bvalid

  • araddr_ack() = arready && arvalid

  • rdata_ack() = rready && rvalid

Instantiation:

inst c: axi4_lite_if::< axi4_lite_pkg::< ADDR_W, DATA_W_BYTES, ID_W > >;

Usage in module definition with modport:

module my_axi4_lite_slave ( aclk: input clock_posedge,
                            aresetn: input reset_sync_low,
                            axi: modport axi4_lite_if::<axi4_lite_pkg::<32, 4, 8>>::slave )
{

}

Note:

The awid, arid, bid and rid signals on the slave* modports are optional. These and are used to connect compatible AXI4-Lite slaves to a full AXI4 interface (AXI ID reflection on slave required).

Packages

axi3_config ### AXI3 configuration definitions
axi3_pkg::<ADDR_W, DATA_W_BYTES, ID_W> ### AXI3 bus package
axi4_config ### AXI4 configuration definitions
axi4_lite_config ### AXI4-Lite configuration definitions
axi4_lite_pkg::<ADDR_W, DATA_W_BYTES, ID_W> ### AXI4-Lite bus package
axi4_pkg::<ADDR_W, DATA_W_BYTES, ID_W, AWUSER_W, WUSER_W, BUSER_W, ARUSER_W, RUSER_W> ### AXI4 bus package
selector_pkg
types A package for pre-defined types

axi3_config

AXI3 configuration definitions

axi3_pkg::<ADDR_W, DATA_W_BYTES, ID_W>

AXI3 bus package

axi4_config

AXI4 configuration definitions

axi4_lite_config

AXI4-Lite configuration definitions

axi4_lite_pkg::<ADDR_W, DATA_W_BYTES, ID_W>

AXI4-Lite bus package

axi4_pkg::<ADDR_W, DATA_W_BYTES, ID_W, AWUSER_W, WUSER_W, BUSER_W, ARUSER_W, RUSER_W>

AXI4 bus package

selector_pkg

types

A package for pre-defined types