std

Veryl Standard Library

Version	0.0.1
Repository	https://github.com/veryl-lang/std
License	MIT OR Apache-2.0

Modules

bin2gray	Converts a binary encoded bit vector to a Gray encoded bit-vector
binary_decoder	A binary decoder.
binary_encoder	A binary encoder.
counter	Value counter
delay	Delay input by configured cycle
gray2bin	Converts a Gray encoded bit vector to a binary encoded bit-vector
gray_counter	Value counter using Gray Encoding
lfsr_galois

Interfaces

Packages

Modules

bin2gray	Converts a binary encoded bit vector to a Gray encoded bit-vector
binary_decoder	A binary decoder.
binary_encoder	A binary encoder.
counter	Value counter
delay	Delay input by configured cycle
gray2bin	Converts a Gray encoded bit vector to a binary encoded bit-vector
gray_counter	Value counter using Gray Encoding
lfsr_galois

bin2gray

Converts a binary encoded bit vector to a Gray encoded bit-vector

Space Complexity: O(WIDTH)
Time Complexity: O(1)

Parameters

WIDTH	u32	Input and output bit vector width

Ports

i_bin	input logic	Input Binary encoded Bit Vector
o_gray	output logic	Output Gray encoded Bit Vector

binary_decoder

A binary decoder.

Converts a bit vector from a binary encoding to a bit vector with a unary encoding.

Parameters

BIN_WIDTH	u32	Width of the input binary vector

Ports

i_en	input logic	Enable Signal. Dynamic power is minimzed when not enabled.
i_bin	input logic	Binary encoded input.
o_unary	output logic	Unary encoded output.

binary_encoder

A binary encoder.

Transforms a unary encoded value into a binary encoding.

Parameters

UNARY_WIDTH	u32	Width of the input unary vector

Ports

i_en	input logic	Enable Signal. Dynamic power is minimzed when not enabled.
i_unary	input logic	Unary encoded input.
o_bin	output logic	Binary encoded output.

counter

Value counter

Parameters

WIDTH	u32	Counter width
MAX_COUNT	bit	Max value of counter
MIN_COUNT	bit	Min value of counter
INITIAL_COUNT	bit	Initial value of counter
WRAP_AROUND	bit	Whether counter is wrap around

Ports

i_clk	input clock	Clock
i_rst	input reset	Reset
i_clear	input logic	Clear counter
i_set	input logic	Set counter to a value
i_set_value	input COUNT	Value used by i_set
i_up	input logic	Count up
i_down	input logic	Count down
o_count	output COUNT	Count value
o_count_next	output COUNT	Count value for the next clock cycle
o_wrap_around	output logic	Indicator for wrap around

delay

Delay input by configured cycle

Parameters

DELAY	u32	Clock cycle of delay
WIDTH	u32	Input/output data width
TYPE	type	Input/output data type

Ports

i_clk	input clock	Clock
i_rst	input reset	Reset
i_d	input TYPE	Input
o_d	output TYPE	Output

gray2bin

Converts a Gray encoded bit vector to a binary encoded bit-vector

Space Complexity: O(WIDTH log WIDTH)
Time Complexity: O(log WIDTH)

Parameters

WIDTH	u32	Input and output bit vector width

Ports

i_gray	input logic	Input Gray encoded Bit Vector
o_bin	output logic	Output binary encoded Bit Vector such that o_bin[k] = ^o_bin[WIDTH-1:k]

gray_counter

Value counter using Gray Encoding

Parameters

WIDTH	u32	Counter width
MAX_COUNT	bit	Max value of counter (in binary)
MIN_COUNT	bit	Min value of counter (in binary)
INITIAL_COUNT	bit	Initial value of counter (in binary)
WRAP_AROUND	bit	Whether counter is wrap around

Ports

i_clk	input logic	Clock
i_rst	input logic	Reset
i_clear	input logic	Clear counter
i_set	input logic	Set counter to a value
i_set_value	input COUNT	Value used by i_set
i_up	input logic	Count up
i_down	input logic	Count down
o_count	output COUNT	Count value
o_count_next	output COUNT	Count value for the next clock cycle
o_wrap_around	output logic	Indicator for wrap around

lfsr_galois

Parameters

SIZE	u32	Size of the LFSR in bits
TAPVEC	tapvec	Bit-vector representing the taps of the LFSR. Default values provided for `SIZE` in range [2, 64]

Ports

i_clk	input clock	Clock
i_en	input logic	Enable - LFSR shifts only when enabled. Active high.
i_set	input logic	Flag to set value of LFSR. Active High.
i_setval	input logic	Value which LFSR is set to when `i_set` is set.
o_val	output logic	LFSR value.