synchronizer
Parameters
| WIDTH | u32 | |
|---|---|---|
| INITIAL_VALUE | bit<WIDTH> | |
| STAGES | u32 |
Clock Domains
| 'd |
|---|
| 's |
Ports
| i_clk | input | 'd | clock | |
|---|---|---|---|---|
| i_rst | input | 'd | reset | |
| i_d | input | 's | logic<WIDTH> | |
| o_d | output | 'd | logic<WIDTH> |
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| WIDTH | u32 | |
|---|---|---|
| INITIAL_VALUE | bit<WIDTH> | |
| STAGES | u32 |
| 'd |
|---|
| 's |
| i_clk | input | 'd | clock | |
|---|---|---|---|---|
| i_rst | input | 'd | reset | |
| i_d | input | 's | logic<WIDTH> | |
| o_d | output | 'd | logic<WIDTH> |