std
Veryl Standard Library
| Version | 0.0.1 |
|---|---|
| Repository | https://github.com/veryl-lang/std |
| License | MIT OR Apache-2.0 |
Modules
| async_fifo::<S> | Asynchronous FIFO |
|---|---|
| async_handshake::<S> | Asynchronous handshake |
| binary_decoder | A binary decoder. |
| binary_encoder | A binary encoder. |
| counter | Value counter |
| countones | |
| delay | Delay input by configured cycle |
| demux | |
| edge_detector | Edge detector |
| fifo | |
| gray_counter | Value counter using Gray Encoding |
| gray_decoder | Converts a Gray encoded bit vector to a binary encoded bit-vector |
| gray_encoder | Converts a binary encoded bit vector to a Gray encoded bit-vector |
| lfsr_galois | |
| mux | |
| onehot | |
| ram |
Module Prototypes
| synchronizer |
|---|
Interfaces
| axi3_if::<PKG> | ### AXI3 bus interface |
|---|---|
| axi4_if::<PKG> | ### AXI4 bus interface |
| axi4_lite_if::<PKG> | ### AXI4-Lite bus interface |
Packages
| axi3_config | ### AXI3 configuration definitions |
|---|---|
| axi3_pkg::<ADDR_W, DATA_W_BYTES, ID_W> | ### AXI3 bus package |
| axi4_config | ### AXI4 configuration definitions |
| axi4_lite_config | ### AXI4-Lite configuration definitions |
| axi4_lite_pkg::<ADDR_W, DATA_W_BYTES, ID_W> | ### AXI4-Lite bus package |
| axi4_pkg::<ADDR_W, DATA_W_BYTES, ID_W, AWUSER_W, WUSER_W, BUSER_W, ARUSER_W, RUSER_W> | ### AXI4 bus package |
| selector_pkg | |
| types | A package for pre-defined types |